Solid-state nonvolatile memories, such as EEPROMs (electrically erasable programmable read only memories) have been used as storage devices for various applications including communication modules, equipment control systems, and consumer electronics products. Progress of these applications increasingly requires higher memory performance in terms of fast access time, high endurance, low power and high storage density.
FIG. 1 illustrates a conventional EEPROM memory device. The memory device 100 has n pages; each page is formed by a row. For example, first row 150 defines first page, second row 160 defines second page, and so on. The memory device 100 has m bytes in each page. For example, first page 150 contains first byte 110 through mth byte 140. Each byte has a number of memory bits. The source terminal of the memory bits are connected to a common line 190 which is coupled to the drain of a source control transistor 191.
In the conventional EEPROM, each byte in the memory device 100 has a dedicated byte select transistor to enable byte accessibility for read, program, and erase operation. For example, transistor 114 is the byte select transistor for byte 110. Therefore the conventional memory device 100 contains n*m memory bytes and n*m byte select transistors.
For a conventional memory device construction such as device 100, dedicated byte select transistors are necessary for byte accessibility. However, these transistors occupy significant silicon estate especially when process technology moves towards smaller pitches. There are endeavors to eliminate the byte select transistors in order to increase array density while having byte accessibility.
U.S. Pat. No. 5,455,790 discloses an EEPROM cell and operation that could realize byte accessibility without byte select transistors. The memory cell is specially constructed to place each byte segment in individually electrically isolated Pwells in N type substrate in order to achieve byte accessibility.
US Patent Application No. 20070140008 discloses another type of EEPROM cell and operation. The cell adopts a special construction that incorporates an integral bit select transistor, which results in a smaller footprint. Again it is built in individually electrically isolated Pwells within a deep Nwell, which is in a P type substrate.
The structure of well isolation, either P-N junction isolation, or dielectric isolation, such as a deep trench, takes a significant extra space and usually involves extra process steps or a change to conventional process integration.
Alternatively, US Patent Application No. 20090279361 discloses a memory configuration to eliminate byte select transistor in an EEPROM array. The byte select transistor is eliminated by separately biasing well and several other control lines to selectively program a byte, word, or page. However, using well bias requires a memory p-well to be isolated from p-substrate, e.g., through a triple well, which modifies conventional process integration and adds process complexity. In its operation, the byte segment source lines, common well line and select lines all need complex biasing scheme in addition to bit lines and word lines, thus adds circuit complexity and memory footprint.
In view of the above problems of byte-addressable EEPROM memory devices, there are needs to improve the density of memory arrays and yet preserve the simplicity and maturity of device structure, memory operation, and manufacturing process.